The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements for improved spacer formation within a semiconductor device.
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large scale integration has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate, source and drain regions for each of the transistors, and in particular the dimensions of the gate, source and drain regions. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size (e.g., width) of the transistor""s gate, and the placement of the source and drain regions there about. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).
As is often the case, however, as the devices shrink in size from one generation to the next, some of the existing fabrication techniques are not precise enough to be used in fabricating the next generation of integrated circuit devices. For example, spacers are used in conventional semiconductor devices to provide alignment of the source and drain regions to the gates in transistors. Minor differences in the shape of the spacers can alter the operational characteristics of the device. This is especially true for integrated circuits that have a plurality of similar devices that are meant to share common operating characteristics. Accordingly, there is a continuing need for more efficient and effective fabrication processes for forming semiconductor gates, spacers and regions that are more precisely controlled.
The present invention provides methods and arrangements that increase the process control during the formation of spacers within a semiconductor device. For example, in accordance with one aspect of the present invention, the spacers are provided on a semiconductor device gate arrangement and used to form lightly doped drain (LDD) regions within a semiconductor device arrangement. In accordance with other aspects of the present invention, the spacers are provided on a polysilicon line within the semiconductor device.
In accordance with one embodiment of the present invention, a method is provided for forming substantially uniformly sized spacers on transistor gate arrangements within a semiconductor device. The method includes forming a plurality of semiconductor device gate arrangements on a top surface of a substrate, such that two of the plurality of semiconductor device gate arrangements are positioned parallel to one another and separated by a defined space. The method includes forming the dielectric layer over at least a portion of each of the two semiconductor device gate arrangements and at least a portion of the defined space. Next, the method includes removing portions of the dielectric layer to form a plurality of spacers. Each of the spacers is physically connected to one of the semiconductor device gate arrangements and the substrate. Thus, because of the topology of the two semiconductor device arrangements, the spacers located within the defined space have a base width that is approximately the same. The method further includes configuring one of the two semiconductor device gate arrangements to control an electrical current between a source region and a drain region formed in the substrate and configuring the remaining one of the two semiconductor device gate arrangements to be non-operational. Thus, the non-operational transistor arrangement is provided for the purpose of controlling the topology and in particular the aspect ratio of the defined space between the operational and non-operational transistor gate arrangements.
In accordance with yet another embodiment of the present invention, a method is provided for controlling the width of a spacer in a semiconductor device arrangement. The method comprises forming an operational semiconductor device gate arrangement on a substrate at a first position, and a non-operational semiconductor device gate arrangement at a second position on a substrate. As such, the operational and non-operational semiconductor device gate arrangements are adjacent to each other but not touching and define a critical space between them. The method includes forming a dielectric layer over at least a portion of the operational and non-operational semiconductor device gate arrangements and within the critical space. The method further includes removing portions of the dielectric layer to form a first spacer that is physically connected to a sidewall of the operational semiconductor device gate arrangement in the substrate. The first spacer extends into the critical space. A second spacer is also formed and is physically connected to a sidewall of the non-operational transistor gate arrangement and the substrate. A second spacer extends into the critical space. As a result of this arrangement, each of the first and second spacers extends into the critical space for substantially the same distance.
In accordance with yet another embodiment of the present invention, a semiconductor device is provided that includes a substrate, a first semiconductor device gate arrangement, a second semiconductor device gate arrangement, a first dielectric spacer, and a second dielectric spacer. Within the substrate there is a source region and a drain region. The first semiconductor device gate arrangement has a first height and a first width and is formed on the substrate with the first width being centered over a first location on the substrate. The first semiconductor device gate arrangement is further configured to control an electrical current between the source region and the drain region formed in the substrate. The second semiconductor device gate arrangement has a second height and a second width and is formed on the substrate with the second width being centered over a second location on the substrate. The second location is separated from the first location by an initial space. The second semiconductor device gate arrangement is configured to be non-operational. The first dielectric spacer is physically connected to the substrate and a first sidewall of the first semiconductor device gate arrangement. The first sidewall of the first semiconductor device gate arrangement is of the first height and is located within the initial space. The first dielectric spacer has a first spacer width as measured at a base of the first dielectric spacer beginning at the first sidewall of the first transistor gate arrangement and extending into the initial space in a direction of the second location. The second dielectric spacer is physically connected to the substrate and a first sidewall of the second semiconductor device gate arrangement. The first sidewall of the second transistor gate arrangement has a second height and is located within the initial space. The second dielectric spacer has a second spacer width as measured at the base of the second dielectric spacer beginning at the first sidewall of the second semiconductor device gate arrangement and extending into the initial space in the direction of the first location. Thus, based on the arrangement of the first and second semiconductor device gate arrangements, and the resulting topology, the aspect ratio of the initial space causes the first spacer width and the second spacer width to be approximately the same.
In accordance with certain embodiments of the present invention, the first semiconductor device gate arrangement includes a thin oxide layer formed on the substrate and a gate conductor including polysilicon formed on the thin oxide layer.
In accordance with yet other embodiments of the present invention, the first dielectric spacer comprises silicon oxide, silicon nitride, silicon-oxynitride, and/or silicon oxime.
In accordance with yet another aspect of the present invention, a method is provided for controlling the formation of spacers on a plurality of polysilicon lines that are formed within a semiconductor device. The method includes forming a plurality of polysilicon lines on a top surface of a substrate. The method further includes forming at least one dummy polysilicon line on the substrate, such that the dummy polysilicon line is substantially parallel to at least a portion of one of the polysilicon lines and is separated from that portion of the polysilicon line by a defined space that defined an aspect ratio. The method further includes covering the polysilicon lines and the dummy polysilicon line along with the top surface of the substrate below the defined space with at least one dielectric layer. The method further includes removing portions of the dielectric layer to form a plurality of separate dielectric spacers and a plurality of separate dummy dielectric spacers. Each of the dielectric spacers is connected to a sidewall of one of the plurality of polysilicon lines and the substrate. Each of the separate dummy dielectric spacers is connected to one of the dummy polysilicon lines and the substrate. Thus, because of the aspect ratio, the width of the dielectric spacers on the sidewalls of the polysilicon lines is more precisely controlled.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.